The Tutorial Programme will take place on September 11. Separate registration is required to participate into this separate programme.
Find more information here

13.30 - Tutorial 1: Fundamentals of cleaning

P. Mertens, imec

This is a course for the absolute beginner in the field.
Required pre-knowledge is general Master-degree level of physics and chemistry.
The general concept of cleaning processes (for any kind of surface) is explained.
fundamental aspects of attraction/bonding between contaminants and surfaces.
How to remove such contaminants.
Role and choice of fluid phase (liquid versus gas…) basic solvent, and specific additives…


14.40 - Tutorial 2: Cleaning and Passivation of SiGe Surfaces

A. Muscat, University of Arizona

The alloy silicon-germanium (SiGe) is currently used in advanced IC technology.
The chemistries of Si and Ge often parallel what one would expect from two atoms in the same column of the periodic table, yet there are several examples where surface structure and electronic effects yield dramatically different outcomes. This tutorial compares and contrasts the surface chemistry of Si, Ge, and SiGe primarily in wet solutions. We will look at the mechanisms for etching, termination, and passivation to develop an understanding of the observed surface reactivity.


15.40 - Coffee Break


16.00 - Tutorial 3: Update on state-of the art Cleaning and surface preparation of III-V semiconductor surfaces

D. van Dorp, imec

This course introduces the state-of-the art know how for the wet-chemical processing of III-V and Ge based channel materials. The small dimensions of FinFET, or Gate-All-Around structures, requires an etching control from nanometer to (sub)atomic-layer-scale. The increased complexity of material properties (e.g. the solubility of group III versus group V oxides or GeO2 versus GeOx oxides, impact of cations on the dissolution mechanism, electroless mechanisms) makes the design of suitable wet chemical etchants quite challenging. The major part of the course focuses on updates of latest findings on etching behaviour and mechanisms in acidic solutions in the low etch rate range. Applications of the work in the field of layer selective etching, trimming, recess etching, smoothening, oxide, defect revealing and (sub)surface damage removal will be shown.

17.00 - Tutorial 4: Post-etch residue removal and surface preparation in BEOL interconnect 

Quoc Tan Le, imec

After a brief introduction to the porous low-dielectric constant materials used in back-end-of-line (BEOL) interconnect, this course mainly focuses on the effect of the plasma patterning of low-k and subsequent wet cleans on the low-k stability and removal of post-etch residues. For patterning of TiN hard mask/porous dielectric structures using fluorocarbon plasmas, fluorine-containing post-etch residues are typically detected on both the top surface and dielectric trench/via sidewall and bottom. Optimized chemical solutions or mixtures to be selected for wet clean process should remove post-etch residues without affecting the trench/via CD, and have no/little impact on properties of the dielectric materials as well as the metals exposed to the wet clean.